Wednesday December 13 , 2017

Introduction to Logic Analyzer

The use and operation of logic analyzers are for testing and trouble shooting microprocessors-based systems.

 

Introduction:

 

We normally use a logic analyzer whenever:

1. We need to see a number of signals at once.

3. We need to trigger on a pattern of highs and lows on several linens and see the result.

 

Logic analyzers are particularly useful when we are looking at time relationships of data on a bus e.g. a microprocessor address, data, or control bus.

 

Logic analyzers are two analyzers in the same time:

 

1. Timing analyzer.

2. State analyzer.

 

Timing analyzer:

 

A timing analyzer is the part of a logic analyzer that is analogous to an oscilloscope. The timing analyzer displays information in the same general form as a scope, with the horizontal axis representing time and the vertical axis as voltage amplitude. Because the waveforms on both instruments are time-dependent, the displays is said to be in the "time domain".

A timing analyzer works by sampling the input wave forms to determine whether they are high or low. It cares about only one voltage threshold The timing analyzer asynchronously samples the system under test. It has an internal clock to control sampling.

 

Triggering the timing analyzer:

 

"Triggering" in logic analyzer is often called "trace point": the logic analyzer continuously captures data and stops the acquisition after the trace point is found to display the data. A logic analyzer can show information after the trace point. Many analyzers trigger on a pattern of highs and lows across input lines. Edge triggering is included in logic analyzers. It allows, e.g. capturing data as the system under test is clocked.

 

Transitional sampling:

 

Transitional timing uses memory efficiently; we use a "transition detector" at the input of the timing analyzer. Timing analyzer will only store those samples which are preceded by a transition together with the elapsed time from the last transition. No memory is used if there is no activity at the input.

 

Glitch capture:

 

In the case of an analyzer, a glitch is defined as any transition that crosses logic threshold more than once between samples the analyzer keep track of all multiple transition between samples and displays them as glitches.

 

State analyzer:

 

A "state" for a logic circuit is a sample of a bus or line when its data is valid .logic state analyzers capture and store information from digital systems.

The major difference between a timing and state analyzer is that the timing analyzer has an internal clock to control sampling, so it asynchronously samples the system under test. On other hand a state analyzer synchronously samples the system since it gets its sampling clock from the digital system under test.

Logic state analyzers are primarily used to assist in software debugging by tracing and displaying the state flow in an algorithmic state machine such as microcomputer.

All operations in an algorithmic state machine occur in synchronism with a system clock which is used to capture, and along with other control signal which are also synchronous with the system clock, to qualify the type of information stored and displays. Information of state logic analyzers may be displayed in a variety of ways among them:

1. state-flow binary and grouped binary.

2. state-flow hexadecimal format.

3. state-flow dissembled format.

As a rule of thumb, you might remember to use a state analyzer to check "what" happened on a bus and a timing analyzer to see "when" it happened. Therefore, state analyzer generally displays data in a listing format and a timing analyzer displays data as waveform diagram.

 

Triggering the state analyzer:

 

a state analyzer gives the capability to qualify the data we want to store . If we are looking for a specific pattern of highs and lows on the address bus, we can tell the analyzer to start storing when it finds the pattern and to continue storing until memory is full.

Disassembly:

Most logic analyzer makers have designed dissemblers or inverse assembler, the job of these packages is to translate the hex codes into assembly code to make them easier to read.

 

Sequence levels:

 

State analyzer have "sequence levels" that did triggering and storage, sequence levels allow you to qualify storage more accurately than a single trigger point

Sequence levels usually look something like:

1. Find XXXX

Else on XXXX go to level Y.

2. Then find XXXX

Else on XXXX go to level Y.

3. Trigger on XXXX.

 

Sequence levels make possible selective storing. Selective storage means storing only a portion of a larger data stream this saves memory and time

 

 

Front Panel Organization

The functional areas of the front panel are: display, menu, keypad, cursor, roll and disk drive.

 

Cursor: The cursor is a movable indicator on display that allow you to access desired fields in each menu the KNOB moves the cursor to the field you activate the field by pressing the SELECT key.

 

Keypad: The Keypad allows you to start and stop data acquisition as well as enter alphanumeric data. Also, in the Keypad area there are the DON'T CARE and CLEAR ENTRY keys.

 

Roll: Roll keys define which way the KNOB will move the displayed data. You will use the roll keys and the KNOB to roll displayed data up/down or left/right to view data that is off screen.

 

Menu: The Menu area contains Keys that give you access to four major menus of logic analyzer:

 

1. Format: select the timing /state format specification menus where you assign names to channels.

2. Trace: specify how and when each analyzer type will acquire data for your measurement.

3. Display: choose how the acquired data will be displayed.

4. I/O: Access disk drive function and set up the analyzer for use with a printer or controller.

 

Display: The display shows you the menu for configuring the logic analyzer and the results of your measurements.

 

Disk Drive: The logic analyzer uses the disk drive every time you turn on the logic analyzer to load its operating system. You can also use the disk drive to store instrument configurations, and acquired data.

 

Experiment 1: Familiarization with HP 165 IB logic analyzer

The objective of this experiment is to have the reader familiar with common pop up menus of a logic analyzer. The following figure illustrates the front panel organization of HP1651B logic analyzer.

 

 

 

Procedure 1.1: Use of the Front Panel

1. Turn on the logic analyzer.

2. Turn the KNOB and watch the cursor move from field to field.

3. Read out the system configuration menu.

4. Place the cursor on the MACHINE field and press SELECT you will see the following pop-up menu.

5. Place the cursor on the field named DONE and press SELECT you go out.

6. Place either the FORMAT, TRACE or DISPLAY key.

7. Place the cursor on the field in the upper left corner and press SELECT.

8. Place the cursor on system in the pop-up and press SELECT you will now be back in the system configuration menu.

 

Procedure 1.2: Switching between analyzers

 

1. Rotate the KNOB until the cursor is on the OFF field in the analyzer.

2 field, then press SELECT.

3. Place the cursor on state and press SELECT.

4. Press the TRACE key.

5. Place the cursor in the field in the upper left cursor of the menu and press SELECT.

6. Move the cursor to the other analyzer (machine) and press SELECT.

 

Procedure 1.3: Alpha entry pop-up menu

 

1. Get back to the system configuration menu.

2. Rotate the KNOB until the cursor is over MACHINE 1 and press SELECT.

3. Rotate the KNOB, and move the cursor so that it is on the L and press SELECT.

4. Repeat steps 4 more times selecting E, A, R and N Procedure 1.4: Changing alpha entry.

5. Press the left/right Roll key.

6. Rotate the KNOB to place the under-score marker under the desired character.

7. Press the left/right Roll again.

8. Press the CLEAR ENTRY key to erase the entire entry.

9. Press the DON'T CARE key to replace a character with a space.

 

Procedure 1.5: Setting Pod threshold

 

1. Select either the TIMING or STATE format specification menu by pressing the FORMAT key.

2. Rotate the KNOB to place the cursor in the TTL field of any pod displayed and press SELECT.

3. Place the cursor on USER DEFINED and press SELECT.

4. Enter 5 from the keypad.

5. Press the CHS (change sign) key.

 

Procedure 1.6: Timing traces specification

 

1. Select the TIMING TRACE specification menu by pressing TRACE key.

2. Rotate the KNOB to place the cursor in the 30 ns box and press SELECT.

3. Enter a new value to replace 30 with the keypad.

4. Close the pop-up menu by pressing SELECT.

 

Procedure 1.7: Assigning bits to pods

Note:

• Asterisk indicate assigned bit

• Period indicate un-assigned bit

 

1. Select either the TIMING or STATE format specification menu.

2. Place the cursor on one of the bit assignment field and press SELECT.

3. Rotate the KNOB to place the cursor on one of the asterisks or periods in the pop-up and press SELECT you will notice how the bit assignment toggles to the opposite state of what it was before pressing SELECT.           

4. Close the pop-up by placing the cursor on done and pressing SELECT.

 

Procedure 1.8: Specifying Timing TRCE Patterns

 

1. Press the TRACE key.

2. Find EDGE field and press SELECT.

3. Place the cursor one of the unsigned bit periods and press SELECT once.

4. Move the cursor to get another unassigned bit period and press SELECT twice.

5. Move the cursor to get another unassigned bit period and press SELECT three times.

6. Place the cursor on done and press SELECT.

Note:

Selects a positive going edge () Selects a negative going edge () Select either edge ().

 

Procedure 1.10: Assigning pods

 

1. Get the system configuration menu.

2. Place the cursor on one of the pad fields on the right side of the display and press SELECT.

3. Place the cursor on Analyzer 1 and press SELECT.

 

Experiment 2: Using the timing analyzer

 

The objective of this experiment is to introduce the student to the use of logic analyzer as a timing analyzer. In particular, he has to learn how to

1. Specify a timing analyzer.

2. Assign pods.

3. Assign bits.

4. Assign labels.

5. Specify a trigger condition.

6. Acquire data.

7. Configure the display.

Required equipments

1. HP 1651B logic analyzer.

2. 6811 Heath kit microprocessor development kit.

 

Procedure 2.1: Use of timing analyzer for testing 6811 development kit

 

1. Get the system configuration menu on screen.

2. Change analyzer 1 type to timing.

3. Name analyzer 1 “6811TEST”.

4. Assign pod l & 2 to analyzer 1.

5. Connect the probes to the target system.

6. Display the TIMING format specification menu.

7. Name pod 1 labels ADDR and pod 3 pin 14 & 15 labels to R & W respectively.

8. Assign the channels connected to the input signals (address lines and R/W lines).

9. Use the trace menu to configure triggering condition.

10. Set the trigger when address pattern = 0000 H and trace armed by RUN.

11. Press the RUN key to acquire the data.

12. Enter the development kit sample program and run it.

13. Use the TIMING waveforms menu to display the acquired data.

14. The X and O are used to find timing from the trigger point the v indicates the trace point, the vertical dotted line indicate the trigger point.

15. Place the cursor on sec/div and press SELECT.

16. Rotate the KNOB for best resolution.

17. Place the cursor on the X to trig field and press SELECT.

18. Rotate the KNOB to place X marker on the edge of waveform ADDR3.

19. Place the cursor at the O to trig and press select and place the O marker on the edge of waveform ADDR3.

20. Perform X to O time measurements.

 

Experiment 3: Using the state analyzer

 

The objective of this experiment is to introduce the use of logic analyzer as a state analyzer.

1. Specify a state analyzer.

2. Assign pods.

3. Assign labels.

4. Connect probes.

5. Assign bits.

6. Specify a trigger condition.

7. Acquire data.

8. Interpret the state listing.

 Required equipment

1. HP 1651B logic analyzer.

2.6811 Heath kit microprocessor development kit.

 

Procedure 3.1: Use of state analyzer for testing 6811 development kit

 

1. Get the system configuration menu on the screen.

2. Change analyzer 1 type to state.

3. Name analyzer 1" 6811 Test".

4. Assign pods 1 and 2 to the state analyzer.

5. Connect the probes to the target system with pod l clock (J clock) to development kit clock to E line on Heath kit in the upper signal connector block.

6. Display the state format specification menu.

7. Name ADDR label to pod 1 and pin 14 * 15 of pod 2 to R and W respectively and data to bit 0:7 of pod 2.

8. Assign the channels connected to the input signals (address lines, data lines and R/W lines).

9. Select the state format specification menu by pressing the format key.

10. Set the J clock to sample on a negative going edge.

11. Select the state trace specification menu by pressing the TRACE key.

12. Set the trigger when address = 0000 H and trace armed by RUN.

13. Press the RUN key to activate the data acquisition.

14. Enter the development kit sample program and run it.

15. Use the display menu to see the state listing menu.

16. Recode the listing on the screen and compare it with that of the sample program.

 

Experiment 4: Using the timing / state analyzer

 

The objective of this experiment is to experiment the simultaneous use of the timing and state analyzers. In particular, the student will learn how to:

1. Trigger one analyzer with the other.

2. Time correlate measurement data.

3. Interpret the mixed-mode display. 

 

Procedure 4.1

 

1. Use the system menu to configure analyzer 1 as a state analyzer.

2. Configure the state format specification menu to assign pod 1 to analyzer 1 and assign address to pod 1.

3. Use the state trace specification menu to configure the triggering condition, choose to trigger when address pattern= 0000 H and trace armed by RUN.

4. Connect the logic analyzer pod 1 probes 0 through 15 to address lines pod 1 , CLK (J clock) to the kit clock signal.

5. Configure analyzer 2 as a timing analyzer.

6. Connect the probes of pod 2 pin 14 & 15 to R and W respectively.

7. Use the timing format specification menu to assign pod2 to analyzer 2 and R and W to pin 14& 15.

8. Display the timing trace specification menu.

9. Place the cursor on the armed by field and press SELECT.

10. Place the cursor on the state analyzer (analyzer 1) option in the pop-up menu and press SELECT.

11. Display the state trace specification menu.

12. Place the cursor in the field just below count on the right side of the display and press SELECT.

13. Place the cursor on the time option and press SELECT.

14. Press RUN.

 

 Entering programs:

 

1. Press the RESET key.

2. Press the EXM MEM key.

3. Enter the starting address in hex. (Format e.g. 0000).

4. Type in the byte to be stored e.g. 86.

5. The address is automatically stepped to the next address.

6. Enter the next byte to be stored e.g. 55.

7. After you enter the whole program quit by pressing the RPO key.

 

Running programs:

 

1. Press RESET key.

2. Press GO key.

3. Enter the starting address in the hex. Format e.g. 0000.

 

Sample program:

 

Address           Address content          Mnemonics

 

0000                             86                      LDA

0001                             55                       55

0002                             97                      STA

0003                             18                     0018

0004                             4C                     INCA

0005                             7E                      JMP

0006                             00                       00

0007                             02                       02